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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0V ≤ V PWR = V BAT ≤ 40V, -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INTERNAL REGULATORS
V DD Power-Up Time (Until INT High)
t PU_VDD
ms
8.0V ≤ V PWR (32)
VLS Power-Up Time
16V ≤ V PWR (33)
t PU_VDD
–
–
–
–
2.0
2.0
ms
CHARGE PUMP
Charge Pump Oscillator Frequency
F OSC
90
125
190
kHz
Charge Pump Slew
Rate (34)
SR CP
–
100
–
V/ μ s
GATE DRIVE
High-Side Turn-On Time
t ONH
ns
Transition Time from 1.0 to 10V, Load: C = 500pF, Rg = 0, ( Figure 7 )
High-Side Turn-On Delay (35)
Delay from Command to 1.0V, ( Figure 7 )
High-Side Turn-Off Time
Transition Time from 10 to 1.0V, Load: C = 500pF, Rg = 0, ( Figure 8 )
High-Side Turn-Off Delay (35)
Delay from Command to 10V, ( Figure 8 )
Low-Side Turn-On Time
Transition Time from 1.0 to 10V, Load: C = 500pF, Rg = 0, ( Figure 7 )
Low-Side Turn-On Delay (35)
Delay from Command to 1.0V, ( Figure 7 )
Low-Side Turn-Off Time
Transition Time from 10 to 1.0V, Load: C = 500pF, Rg = 0, ( Figure 8 )
Low-Side Turn-Off Delay (35)
Delay from Command to 10V, ( Figure 8 )
t D_ONH
t OFFH
t D_OFFH
t ONL
t D_ONL
t OFFL
t D_OFFL
–
130
–
130
–
130
–
130
20
265
20
265
20
265
20
265
35
386
35
386
35
386
35
386
ns
ns
ns
ns
ns
ns
ns
Same Phase Command Delay Match (36)
Thermal Filter Duration (37)
t D_DIFF
t DUR
-20
8.0
0
–
+20
30
ns
μs
Notes
32. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on V DD .
33.
34.
35.
36.
37.
The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VLS. This
delay includes the expected time for V DD to rise.
The charge pump operating at 12V V bat , 1 μ F pump capacitor, MUR120 diodes and 47 μ F filter capacitor.
These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes
one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and
output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision
block. Synchronization time accounts for up to one clock period of variation. See Figure 6 .
This is the maximum separation or overlap of the High and Low side gate drives due to propagation delays when commanding one ON
and the other OFF simultaneously.
The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
33927
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
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